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The P-type silicon substrate 1 and the N-type doped source region 2 are respectively used for forming a PN junction. The P-type silicon substrate 1 and the N-type doped drain region 3 are used for fabricating a PN junction. The N-type doped source region 2 and the N-type doped drain region 3 are used for forming a PN junction. The gate dielectric layer 4 is used for isolating the gate electrode 5 from the source region 2, the drain region 3, and the PN junction. The gate electrode 5 is used for switching electrons. The gate dielectric layer 4 is generally formed of a silicon oxide layer. The gate electrode 5 is generally formed of a metal layer. The thickness of the gate dielectric layer 4 is between 50 to 200 xc3x85. The thickness of the gate dielectric layer 4 is usually used for determining the operating voltage of the device. The gate dielectric layer 4 is 8e68912320 Auto Translator With Serial Key Free Download Keymacro is a personal assistant with keyboard shortcuts. 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